`default_nettype none

`define CLK_FREQ 27_000_000
`define DIV_CLK_DEFAULT (`CLK_FREQ / 1) // 默认时钟为1hz

module test_right_shift_reg_m (
    input rst_w_ni,
    input clk_w_i,

    output led_red_w_no,
    output led_green_w_no
);
    wire reg_clk_w;

    clk_even_div_m #(
        .DIV_DIV_2_CP_I(`DIV_CLK_DEFAULT / 2)
    ) default_div_i (
        .rst_w_ni(rst_w_ni),
        .clk_w_i  (clk_w_i),

        .clk_w_o(reg_clk_w)
    );

    wire [1:0] data_out_wp;
    wire data_xor = ^data_out_wp;
    wire [1:0] data_in_wp = {data_xor, ~data_xor};

    right_shift_reg_m #(
        .WIDTH_CP_I(5),
        .SHIFT_WIDTH_CP_I(2),
        .INIT_VALUE_CP_I(5'b10011)
    ) shift_reg_i (
        .rst_w_ni(rst_w_ni),
        .clk_w_i(reg_clk_w),
        .shift_en_w_pi(1),
        .data_wp_i(data_in_wp),
        .set_en_w_pi(0),
        .set_wp_i(),

        .data_wp_o(data_out_wp),
        .get_wp_o()
    );

    assign led_red_w_no   = data_out_wp[0];
    assign led_green_w_no = data_out_wp[1];
endmodule
